pll500 - 27/ - 37/ - 47 low power cmos output vcxo family (27mhz to 200mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 01 / 21 /0 4 page 1 features vcxo output for the 27mhz to 200mhz range - pll500 - 27: 27mhz to 65mhz - pll500 - 37: 65mhz to 130mhz - pll500 - 47: 100mhz to 200mhz low phase noise ( - 130 dbc @ 10khz offset). cmos output with oe tri - state control. selectable output drive (standard or high drive). - standard: 12ma drive cap a bility at ttl level. - high: 36ma drive cap a bility at ttl level. fundamental crys tal input . integrated high linearity variable c a pacitors. +/ - 150 ppm pull range, max 5% lin e arity. low jitter (rms): 2.5ps period jitter. 2. 5 - 3.3v operation. available in 8 - pin soic or die. description the pll500 - 27/ - 37/ - 47 are a low cost, high perfor m- ance , low phase noise, and high linearity vcxo fa m- ily for the 27 to 200mhz range, pr o viding less than - 130dbc at 10khz offset. the very low jitter (2.5 ps rms period jitter) makes these chips ideal for appl i- cations requiring voltage co n trolled frequency sources. the ic?s are designed to accept fundame n- tal res o nant mode crystals. pin configuration die pad layout frequency range part # multipli er frequency pll500 - 27 no pll 27 ? 65 mhz pll500 - 37 no pll 65 ? 130 mhz pll500 - 47 no pll 100 ? 200 mhz block diagram xtal osc oe xin xout vcon varicap p l l 5 0 0 - x 7 1 2 3 4 5 6 7 8 xin drivsel^ vcon gnd xout vdd clk oe^ ^: denotes internal pull-up 1 2 3 4 7 6 5 8
pll500 - 27/ - 37/ - 47 low power cmos output vcxo family (27mhz to 200mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 01 / 21 /0 4 page 2 pin and pad description die pad position name pin# x ( m m m) y ( m m m) type description xin 1 94.183 768. 599 i crystal input pin. drivsel 2 94.157 605.029 i output drive select pin. high drive if set to ?0?. low drive if set to ?1?. internal pull - up. v con 3 94.183 331.756 i frequency control voltage input pin. gnd 4 94.193 140.379 p ground pin. clk 5 715. 472 203.866 o output clock pin. vdd 6 715.307 455.726 p vdd power supply pin. oe 7 715.472 626.716 i output enable input pin. disables the output when low. inte r nal pull - up enables output by default if pin is not connected low . xout 8 476.906 888.881 i crystal output pin. ref clock input. electrical specifica tions 1. absolute maximum ratings parameters symbol min. max. units supply voltage range v cc - 0.5 7 v input voltage range v i - 0.5 v cc + 0.5 v output voltage range v o - 0.5 v cc + 0.5 v soldering tempe rature 260 c storage temperature t s - 65 150 c ambient operating temperature 0 70 c exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device and affect prod uct reliability. these conditions represent a stress rating only, and functional operations of the device at these or any other co n ditions above the operational limits noted in this specification is not implied.
pll500 - 27/ - 37/ - 47 low power cmos output vcxo family (27mhz to 200mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 01 / 21 /0 4 page 3 2. ac electrical specifications parameter s symbol conditions min. typ. max. units pll500 - 27 27 65 pll500 - 37 65 130 input crystal frequency pll500 - 47 100 200 mhz 0.8v ~ 2.0v with 10 pf load 1.15 output clock rise/fall time 0.3v ~ 3.0v with 15 pf load 3.7 ns output clock dut y cycle measured @ 1.4v 45 50 55 % short circuit current 50 ma 3. voltage control crystal oscillator parameters symbol conditions min. typ. max. units vcxo stabilization time * t vcxostb from power valid 10 ms vcxo tuning range xtal c 0 /c 1 < 250 300 ppm clk output pullability 0v v con 3.3v 150 ppm vcxo tuning characteristic 100 ppm/v pull range linearity 5 % power supply rejection pwsrr frequency change with v dd varied +/ - 10% - 1 +1 ppm v con pin input impedance 1000 k w v con modulation bw 0v v con 3.3v, - 3db 45 khz note: preliminary specifications still to be characterized. parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. jit ter and phase noise specification parameters conditions min. typ. max. units rms period jitter (1 sigma ? 1000 samples) w ith capacitive decou p ling b e tween vdd and gnd. 2.5 ps phase noise relative to carrier @100hz offset - 80 dbc/hz phase noise relat ive to carrier @1khz offset - 110 dbc/hz phase noise relative to carrier @10khz offset - 130 dbc/hz phase noise relative to carrier @100khz offset - 138 dbc/hz phase noise relative to carrier @1mhz offset - 145 dbc/hz
pll500 - 27/ - 37/ - 47 low power cmos output vcxo family (27mhz to 200mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 01 / 21 /0 4 page 4 5. dc specification p a rameter s sy m bol cond i tions min. typ. max. units f xin = 36mhz, 15pf output load 5 6 f xin = 77mhz, 15 pf output load 10 1 2 supply current, dynamic, with loaded outputs i dd f xin = 155mhz, 1 5 pf output load 1 5 1 8 ma pll500 - 27 n / a pf pll500 - 37 and - 47 : st d drive 15 pf allowable o utput load c a pacitance c l (output) pll500 - 37 and - 47 : high drive 10 pf operating voltage v dd 2.25 3.63 v out put high voltage v oh i oh = - 12ma 2.4 v output low voltage v ol i o l = 12ma 0.4 v output high voltage at cmos level i oh = - 4ma v dd ? 0.4 v standard drive at ttl level 12 17 output drive current high drive at ttl level 36 51 ma short circ uit current 50 ma vcxo control voltage v con 0 3.3 v esd protection human body model 2 000 v 6. crystal specifications parameters sy m bol min. typ. max. units crystal loading ra t ing (v con = 1.65v) c l (xtal) 8.5 pf maximum sustainable drive le vel 200 m w operating drive level 50 m w max c0 for pll500 - 27 3.5 max c0 for pll500 - 37 2.5 max c0 for pll500 - 47 2 pf c0/c1 250 - esr r s 30 w note : the crystal must be such that it oscillates (parallel resonant) at nominal frequency when pre sented a c load as specified above. if the crystal requires more load to be at nominal frequency, the additional load must be added e x ternally. this ho w ever may reduce the pull range.
pll500 - 27/ - 37/ - 47 low power cmos output vcxo family (27mhz to 200mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492 - 0990 fax (510) 492 - 0991 rev 01 / 21 /0 4 page 5 package inform a tion ordering information phaselink corporation, reser ves the right to make changes in its products or specifications, or both at any time without notice. the information fu r- nished by phaselink is believed to be accurate and reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the e x- press written approval of the president of phaselink corporation. c l a 8 pin ( dimensions in mm ) narrow soic symbol min. max. a 1.47 1.73 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 4.95 e 3.80 4.00 h 5.80 6.20 l 0.38 1.27 e 1.27 bsc e h d a 1 e b part number the order number for this device is a combination of the following: device number, package type and operating temperature range pll500-x7 x x temperature c=commercial package s=soic d=die part number order number marking package option p ll500 - 2 7s c p500 - 2 7sc 8 - pin soic (tube) p ll500 - 2 7s c - r p500 - 2 7sc 8 - pin soic (tape and reel) pll500 - 2 7dc p5 00 - 2 7dc die (waffle pack) p ll500 - 37s c p500 - 37sc 8 - pin soic (tube) p ll500 - 37s c - r p500 - 37sc 8 - pin soic (tape and reel) pll500 - 37dc p500 - 37dc die (waffle pack) p ll500 - 47s c p500 - 47sc 8 - pin soic (tube) p ll500 - 47s c - r p500 - 47sc 8 - pin soic (tape and reel) pll500 - 47dc p500 - 47dc die (waffle pack)
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